In order to maximize the usable dynamic range of a receiver (or other system), it is necessary to control the gain of the signal path in that system. In order to optimally set the gain, one must have a clear indication of the amplitude of the signal at the point being optimized. Detecting a sensitive RF signal, without distorting the signal through observation, is a problem to be addressed to allow a robust implementation of such a system.
FIG. 1 illustrates a block diagram of a typical RF receiver 10. The RF receiver 10 will monitor the signal amplitude at several points along the path, and adjust associated gain and attenuation stages accordingly.
A peak detector 12 is typically used to quantify the peak amplitude of a signal. A threshold detector can be considered a simplified sub-component of a peak detector, where the function is simplified to indicate if a given signal is larger or smaller than a particular threshold. A threshold detector can be combined with a control system which manipulates the reference threshold to systematically determine the peak of the signal, thereby achieving the same function of the original peak detector.
A peak detector is a circuit that detects the time varying peak amplitude of an analog signal. As the frequency of these input signals increases, and the precision with which their peak must be quantified increases, this task becomes more difficult to accomplish. Analog peak detectors, utilizing the inherent physical characteristics of transistors to track and capture a peak of a signal, do not perform this task well as speeds increase and signal amplitudes fall. In particular, it is difficult to track small amplitudes in deep submicron technologies using traditional analog circuit topologies due to high inherent offsets and unpredictable, or poorly characterized, sub-threshold device behavior.
Examples of known RF signal peak detectors are provided in the following, each of which is incorporated by reference in its entirety: U.S. Pat. No. 6,977,531, U.S. Pat. No. 7,236,014, and U.S. Pat. No. 7,352,240.
A digital sampling peak detector is attractive for its high precision over analog detection mechanisms, but the introduction of a clock signal in a system requiring high linearity is difficult to manage.
Therefore, it is desirable to provide a sampling detector architecture to monitor sensitive RF signals.